This invention relates to integrated circuits such as programmable integrated circuits, and more particularly, to serial memory interfaces for programmable integrated circuits.
Programmable integrated circuits such as field programmable gate arrays and other programmable logic devices are integrated circuits that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit. When the design process is complete, the tools generate configuration data files. The configuration data is loaded into memory elements on the programmable integrated circuits to configure the programmable integrated circuits to perform the desired custom logic function.
Programmable integrated circuits may be coupled to external memory such as random-access memory. To support high memory bandwidth, an integrated circuit and associated memory may be provided with serial memory interfaces. The serial memory interfaces may be used to send and receive data packets over a serial communications path between the integrated circuit and the associated memory.
Challenges can arise when providing a programmable integrated circuit with a serial memory interface. Different memories may support different serial memory interface protocols. It would be desirable to be able to support multiple serial memory interface protocols to maximize compatibility with these different types of memory.
Latency is also a concern. To ensure successful transmission of data across a serial path between an integrated circuit and a memory, each successfully received packet is acknowledged by sending a corresponding acknowledgement over the serial path. Retransmission buffers are used to store transmitted packets until acknowledgement of successful transmission is received. Memories typically do not include large retransmission buffers. Particularly in environments in which retransmission buffer size is limited, link performance can be significantly reduced in the presence of acknowledgement processing latency, so there is a desire to minimize acknowledgement processing latency.
It would be desirable to be able to provide serial memory interface circuitry for programmable integrated circuits that can address these concerns.